1. Field of the Disclosure
The present disclosure relates in general to semiconductor devices, and more specifically to multi-bit master latches with enhanced fault detection.
2. Description of the Related Art
As consumers demand smaller processing devices, the integrated circuits within the devices also must shrink. As the size of the semiconductor memory devices decreases, the bit cell area also decreases, causing an increase in the possibility of failures induced by soft error rate (SER) and/or single event upset (SEU). SER and SEU can occur, for example, when external energy (such as energy due to alpha particle bombardment) is imparted onto the circuit, causing bit values in a memory, voltage detectors and/or other devices, to change to erroneous values. Therefore, as device geometries continue to shrink, error detection becomes increasingly important. Additionally, it is important to reduce power consumed by error detection so that energy costs are reduced and portable devices can operate for longer time periods between battery recharges.
Flip-flops are often used as the basic storage element in circuit design. When the circuit enters a low power mode the clock signal may be deactivated and the flip-flops may transfer the state to low leakage latches (e.g., a balloon latch). When the power supply is restored to the flip-flop, a signal (e.g., restore, active) may be asserted to transfer the state from the latches back to the flip-flops.